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LSI/CSI
UL
(R)
LS7030
(631) 271-0400 FAX (631) 271-0405 December 2002
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
8 DECADE MULTIPLEXED COUNTER
FEATURES: * DC to 7.5 MHz Count Frequency * Multiplexed BCD and 7 Segment Outputs * DC to 500 kHz Scan Frequency * +4.75V to +15V Operation (VDD-VSS) * Compatible with CMOS Logic * High Input Noise Immunity * Counter Output Latches * Leading Zero Blanking * Low Power Dissipation * All inputs protected * 40 Pin DIP- See Figure 1 DESCRIPTION: The LS7030 is a monolithic, ion implanted MOS Silicon Gate, 8 decade up counter. The circuit includes latches, multiplexer, leading zero blanking and 7 segment data outputs. 8 DECADE UP COUNTER The eight decade ripple through counter increments on the negative edge of the input count pulse. Maximum ripple time is 12s (99999999 to 00000000). Maximum count frequency is 7.5MHz. RESET All decades are reset to zero when Reset input is brought low for a minimum of 4s. The Overflow flip-flop is reset at the same time. Reset must be high for a minimum of 1s before next valid count can be recorded. LATCHES Contents of counter are transferred to latches when LOAD signal is brought low for a minimum of 4s and kept low until a minimum of 12s has elapsed from previous negative edge of count pulse (ripple time). Storage of valid data occurs when LOAD signal is high for a minimum of 1s before next negative edge of count pulse or reset. Data is transferred for Overflow flip-flop to Overflow latch at the same time. SCAN OSCILLATOR AND COUNTER The scan counter is driven by an internal oscillator whose frequency is determined by a capacitor connected between Oscillator input and Scan input. An external scan clock applied to Scan input can also drive the scan counter. Scan counter advances on negative edge of scan clock. The counter scans from MSD to LSD. When Scan Reset input is brought high the scan counter is forced to MSD state. Internal synchonization guarantees proper scanning no matter when Scan Reset is brought low relative to scan clock. Maximum scan frequency is 500kHz. DECIMAL POINT A high at the Decimal Point input resets the Blanking flip-flop causing the display to unblank. Decimal Point should be brought high at start of digit time which has active Decimal Point.
7030-121102-1
CONNECTION DIAGRAM - TOP VIEW SCAN RESET INPUT MSD STROBE 8 STROBE 7 STROBE 6 DIGIT STROBE OUTPUTS STROBE 5 STROBE 4 STROBE 3 STROBE 2 LSD STROBE 1 DECIMAL POINT INPUT BLANK OUTPUT OVERFLOW OUTPUT OVERFLOW INPUT DECADE 6 OUTPUT, DECADE 7 OUTPUT, DECADE 6 OUTPUT, D8 D7 D6 B8 BCD DATA OUTPUTS B4 B2 B1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LS7030 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OSC. INPUT SCAN INPUT LAMP TEST INPUT a b N.C. c d COUNT INPUT e f g TEST COUNT INPUT, DIGITS 3 - 8 V SS V GG N.C. N.C. V DD RESET COUNTER INPUT LOAD LATCH INPUT SEGMENT OUTPUTS SEGMENT OUTPUTS
DIGIT STROBES Timing of Digit Strobes is arranged such that both edges of strobe are guardbanded by a minimum 400ns within valid BCD data when scan frequency is 100kHz or less. The guardband is a minimum of 200ns at 250kHz scan frequency. At 500kHz only negative edge of Strobe is guaranteed to be within valid BCD data by a minimum 200ns. OVERFLOW The Overflow flip-flop sets on the first negative transition of the Overflow Input and remains set until Reset is brought low. Data is transferred from Overflow flip-flop to Overflow Latch when Load is brought low. A high at the Overflow Latch causes display to unblank. Overflow Output is output of Overflow Latch. MSB outputs of Decades 6, 7, 8 are available for use as Overflow Input. BLANKING Leading zero blanking is employed. At start of each MSD to LSD scan, display is blanked until a nonzero digit or active decimal point is encountered. Displaly unblanks during LSD time and for a whole scan when Overflow output is high. When Scan Reset is applied, display blanks to prevent display damage. Blanking information is available at Blank output and is incorporated into 7 segment information.
LSI
FIGURE 1
BCD and 7 SEGMENT DATA Data is available in BCD and 7 segment format. BCD data can be demultiplexed using Digit Strobes as latch enable signals. POWER SUPPLIES +4.75 Volts to +15 Volts single power supply operation is obtained when VGG and VDD are tied together. Inputs and outputs are CMOS compatible and Minimum Input Noise Immunity of 25% of power supply is guaranteed except for Test Count Input. (Inputs are TTL compatible at +4.75V to +5.25V operation.) MAXIMUM RATINGS PARAMETER Storage Temperature Operating Temperature Voltage (any pin to Vss) SYMBOL Tstg TA Vmax VALUE -65 to +150 -25 to +70 -30 to +0.5
With VGG at -12V, VDD at OV and Vss at +5V, all inputs are TTL and CMOS compatible. All outputs are CMOS compatible and BCD and BLANK outputs also provide standard TTL compatibility. In addition, Overflow Output is low power TTL compatible. In either mode outputs swing between VDD and Vss.
UNITS C C V
DC ELECTRICAL CHARACTERISTICS (VDD = VGG= OV, Vss = +4.75 to +15V, -25C TA +70C unless otherwise specified.) PARAMETER Operating Supply Current (fC = 7.5MHz) Input Noise Immunity Low and High Test Count Input D6, D7, D8 OF, BCD Blank (See Note 1) SYMBOL Idds MIN MAX 15 UNITS mA
Vni Vil Vih Vol Voh
25% (Vss-VDD) Vss - 20 Vss - 1.0 Vss - 1.0
Vss - 3.95 Vss +0.2 -
V V V V V
{
Output Voltage "0" Output Voltage "1" Output Voltage "0" (sinking 10A) Output Voltage "1" Vss = 4.75 (Voh = Vss - 0.5V) (Voh = Vss - 1V) (Voh = Vss - 4V) Vss = 10V (Voh = Vss - 2V) (Voh = Vss - 3V) Vss = 15V (Voh = Vss - 2V) (Voh = Vss - 3V)
Vol
-
+0.5
V
Segment and Strobe Outputs (See Note 2)
-
0.05 0.25 0.90 2.0 3.0 3.0 4.5
-
mA mA mA mA mA mA mA
NOTE 1: Current Sink = Same as segment and strobe outputs. Current Source = N/A at Voh = Vss -.5V for Vss = +4.75V 35A at Voh = Vss -1V for Vss = +4.75V 40% of segment and strobe outputs at all other specified operating points. NOTE 2: Limit segment current to 4.5mA maximum. Limit strobe current to 6mA maximum. The following inputs have internal pull down resistors to VDD with maximum sink current of 5A at Vss input. Scan Reset Test Count Count Decimal Point Overflow Lamp Test
SCAN OSCILLATOR CAPACITANCE 50pF 100pF 470pF 750pF 2000pF
7030-110201-2
TYPICAL OSCILLATOR FREQUENCY 4.75V 10V 15V 40.0 kHz 24.2kHz 22.2 kHz 22.2 kHz 14.8kHz 13.8 kHz 5.0 kHz 3.6kHz 3.5 kHz 3.3 kHz 2.4kHz 2.2 kHz 1.3 kHz 0.91kHz 0.85 kHz
ELECTRICAL CHARACTERISTICS: (VDD = VGG = OV, Vss = +4.75 to +15V, -25C TA +70C unless otherwise specified.) PARAMETER Count test and Count frequency (Vss = +5V 5%) (Vss = +10V) (Vss = +15V) Scan frequency Count Pulse Width (Vss = +5V 5%) (Vss = +10V) (Vss = +15V) Count Ripple Time Load Pulse Width Load Removal Tme Reset Pulse Width Reset Removal Time Rise and fall time Count Pulse Reset Pulse test Count Pulse *Strobe Guard Band time (fSC 100kHz) *Strobe Guard Band time (100kHz fSC 250kHz) *Strobe Guard Band time (250kHz fSC 500kHz) negative edge only SYMBOL fc, ftc fc, ftc fc, ftc fsc MIN DC DC DC DC MAX 7.5 6 5 500 UNITS MHz MHz MHz kHz
tcpw tcpw tcpw tcr tlpw tlr trpw trr
66 83 100 4 4 -
12 1 1
ns ns ns s s s s s
trfc trfr trftc tgb tgb tgb
400 200 200
4 4 80 -
s s s ns ns ns
a
f
b g
BCD
tgb
tgb
e
d
c
STROBE FIGURE 2. GUARD BANDED STROBE
TTL COMPATIBLE OUTPUTS: POWER SUPPLIES: Vss = +5V 5%, VDD = 0V, VGG = -12V 5% OUTPUT LEVELS: "1" Level Vss - 0.5V (sourcing 100A) "0" Level 0.4V (sinking 1.6mA) "1" Level Vss - 0.5V (sourcing 40A) "0" Level 0.4V (sinking .18mA)
FIGURE 3. SEVEN SEGMENT FONT
} }
BLANK AND BCD DATA OUTPUTS
OVERFLOW OUTPUT
All other outputs as specified for single power supply, Vss = + 15V, operation. Inputs as specified for single power supply, Vss = +5V 5% operation.
The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use.
7030-110601-3
DECIMAL POINT INPUT SCAN RESET INPUT (RESET TO MSD) 1 9 8 7 6 5 4 3 2 BLANKING F/F S 38 LAMP TEST INPUT R Q 11 BLANK OUT 10 8 DIGIT STROBE OUTPUTS 26 VGG 23 VDD 27 Vss
LSD OUTPUT BUFFERS
MSD
OSC. INPUT
40
NZ OSCILLATOR OR BUFFER R 8 STATE STATIC SCAN COUNTER & DECODED C LSD a b SEVEN SEGMENT c DECODER d e f 7 4 B1 B2 B4 B8 B1 B2 B4 B8 12 48 G MUX GATE G 12 48 MUX GATE 12 48 G MUX GATE G 5 B1 B2 B4 B8 12 48 MUX GATE G 12 48 MUX GATE G 6 B1 B2 B4 B8 12 48 MUX GATE B1 B2 B4 B8 12 48 G MUX GATE B1 DATA OUTPUT B2 BUFFER B4 B8 20 19 18 17 BCD DATA OUTPUT g 37 36 34 SEVEN SEGMENT 33 DATA 31 OUT 30 29
MSD
SCAN INPUT
39 8
1
2
3
12 48 G MUX GATE
12 OVERFLOW OUTPUT 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 4 BIT LATCH ST 1 BIT LATCH
ST
LOAD LATCH INPUT 21
13 OVERFLOW INPUT COUNT INPUT 32 RESET INPUT 22 1248 C BCD COUNTER R 1248 C BCD COUNTER R 1248 C BCD COUNTER R 1248 C BCD COUNTER R 1248 C BCD COUNTER R 124 8 C BCD COUNTER R 1248 C BCD COUNTER R 1248 C BCD COUNTER R C R
OVFLW F/F
28 TEST COUNT INPUT
16
15 D7 OUTPUT
14 D8 OUTPUT
FIGURE 4. LS7030 BLOCK DIAGRAM
D6 OUTPUT

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